/*=============================================================================
# FileName    : lcd_top.v
# Author      : author
# Email       : email@email.com
# Description :
# Version     : 1.0
# LastChange  : 2016-03-28 17:34:32
# ChangeLog   :
=============================================================================*/

`timescale  1 ns/1 ps

module lcd(
		input			clk,
		input			rst,
	 
		input	wire		JTRST_n       ,
		input	wire		JTCK          ,
		input	wire		JTDI          ,
		input	wire		JTMS          ,
		output	wire		JTDO          ,	
	 
	 	//////////////// FLASH PIN 
		output	wire		FLASH_SCK     ,	
		output	wire		FLASH_CS_n    ,	
		output	wire		FLASH_IO0_SI  ,	
		input   wire		FLASH_IO1_SO  ,
		
		output	wire		mcu_init_flag ,
		
		output	wire	[7:0]	port_a,
	
		output		[31:0]	tout  	
		);

wire	[31:0]	core_tout;

///////////////////////////////////////////////////////////////
alta_mcu_top    alta_mcu_topEx01
(
		.CLK			(clk),
		.POR_n			(rst),
		.EXT_CPU_RST_n          (1'b1),
		.O_INI_IP		(mcu_init_flag),

		.JTRST_n                (1'b1),
		.JTCK                   (JTCK),
		.JTDI                   (JTDI),
		.JTMS                   (JTMS),
		.JTDO                   (JTDO),

		.FLASH_BIAS		(24'hB1CE6),

		.FLASH_SCK		(FLASH_SCK),
		.FLASH_CS_n		(FLASH_CS_n),

		.FLASH_IO0_SI		(FLASH_IO0_SI),
		.FLASH_IO0_SI_i		(1'b0),
		.FLASH_SI_OE		(),

		.FLASH_IO1_SO		(),
		.FLASH_IO1_SO_i		(FLASH_IO1_SO),
		.FLASH_SO_OE		(),

		.FLASH_IO2_WPn		(),
		.FLASH_IO2_WPn_i	(1'b1),
		.WPn_IO2_OE		(),

		.FLASH_IO3_HOLDn	(),
		.FLASH_IO3_HOLDn_i	(1'b1),
		.HOLDn_IO3_OE		(),
		
		.EXT_RAM_EN		(1'b0),
		.EXT_RAM_WR		(),
		.EXT_RAM_ADDR		(),
		.EXT_RAM_BYTE_EN	(),
		.EXT_RAM_WDATA		(),
		.EXT_RAM_RDATA		(),

		.HRESP_EXT		(2'b00),
//		.HREADY_OUT_EXT		(   hready_out                  ),
//		.HRDATA_EXT		(   hrdata                      ),
//		.HTRANS_EXT		(   htrans                      ),
//		.HADDR_EXT		(   haddr                       ),
//		.HWRITE_EXT		(   hwrite                      ),
//		.HSEL_EXT		(   hsel                        ),
//		.HWDATA_EXT		(   hwdata                      ),
//		.HSIZE_EXT		(   hsize                       ),
//		.HREADY_IN_EXT		(   hready_in                   ),

		.UART_RXD		(),
		.UART_CTS_n		(),
		.UART_TXD		(),
		.UART_RTS_n		(),

		.GPIO0_I                (),
		.GPIO0_O                (port_a),
		.nGPEN0                 (),
		.GPIO1_I                (),
		.GPIO1_O                (),
		.nGPEN1                 (),
		.GPIO2_I                (),
		.GPIO2_O                (),
		.nGPEN2                 (),

		.tout			(core_tout)
) ;

assign tout = core_tout;

endmodule
